Arrangement of memory devices in a multi-rank memory module

ABSTRACT

A multi-rank memory module is operable in a memory system with a memory controller. The memory module according to one embodiment comprises at least one module board, memory devices organized in three ranks, and at least one register device providing control/address signals to the memory devices. Arrangement of the ranks on the at least one module board are made to balance memory device loadings on the C/A signals, and data/strobe signal hubs are designed to provide better alignment of different data bits in a data signal and to reduce reflection from discrete components disposed near an edge of the module board, resulting in improved signal quality and integrity.

CLAIM OF PRIORITY

The present application claims priority to U.S. Provisional ApplicationNo. 61/682,249 filed on Aug. 11, 2012, which is incorporated herein byreference in its entirety.

FIELD

The disclosure herein is related generally to memory modules, and moreparticularly to multi-rank memory modules.

DESCRIPTION OF RELATED ART

The disclosure herein is related generally to memory modules, and moreparticularly to multi-rank memory modules.

BACKGROUND

Computer systems often utilize modules comprising one or more printedcircuit boards (PCBs). Each PCB has one or more components (e.g.,integrated circuits or ICs) mounted thereon, and the components can bemounted on one side or on both sides of the PCB. The one or more PCBsalso include module connectors for coupling the components in the moduleto the computer system. For a memory module, the components may includememory devices that are organized in ranks such that the memory devicesin a rank are selectable by a single chip select signal and, whenselected, communicate respective data bits of a data signal. The memorymodule may also include one or more register devices to provideregistered control/address signals to the memory devices. When thememory module has multiple ranks of memory devices, it is important thatthe multiple ranks of memory devices and their connections to respectivemodule connectors are properly arranged to insure the quality andintegrity of the data signals communicated thereto and therefrom. It isalso helpful to balance their loads on the registered C/A signals.

SUMMARY

A multi-rank memory module is operable in a memory system with a memorycontroller. The memory module according to one embodiment comprises amodule board having a first side and an opposing second side; and memorydevices organized in three ranks. The memory devices in a first rank ofthe three ranks are all mounted on the first side, the memory devices ina second rank of the three ranks are all mounted on the second side, andthe memory devices in a third rank of the three ranks include somememory devices mounted on the first side, and some memory devicesmounted on the second side.

In certain embodiments, the multi-rank memory module further comprisesmodule connectors along an edge of the module board and data/strobesignal hubs disposed away from the edge of the module board. The moduleconnectors include data/strobe signal pins and control/address (C/A)signal pins, and each respective data/strobe signal hub is coupled to arespective data/strobe signal pin and to a respective set of first,second and third memory devices in different ranks. The respectivedata/strobe signal hub is positioned to reduce difference in lengths offirst, second and third signal paths. The first signal path is betweenthe respective data/strobe signal pin and the first memory device, thesecond signal path is between the respective signal pin and the secondmemory device, and the third signal path is between the respectivedata/strobe signal pin and the third memory device. Thus, betteralignment of different data bits in a data signal is achieved. Thedata/strobe signal hubs are positioned away from the edge of the moduleboard to reduce reflection from discreet components disposed near theedge of the module board, resulting in improved signal quality andintegrity.

In certain embodiments, the data/strobe signal hubs include a firstsignal hub and a second signal hub coupled to respective ones of firstdata/strobe signal pin and second data/strobe signal pin. The multi-rankmemory module further comprises a first signal trace between the firstdata/strobe signal pin and the first signal hub, and a second signaltrace between the second data/strobe signal pin and the second signalhub. One of the first and second signal traces being routed to increaseits length so as to reduce difference in lengths between the firstsignal trace and the second signal trace.

In certain embodiments, the multi-rank memory module further comprises afirst register providing registered control/address (C/A) signals tomemory devices in the first and second ranks, and a second registerproviding registered C/A signals to memory devices in the third rank.

In another embodiment, a multi-rank memory module comprises a mainmodule board having a first side and an opposing second side, a firstdaughterboard coupled to the main module board and disposed on the firstside of the main module board, and a second daughterboard coupled to themain module board and disposed on the second side of the main moduleboard. The memory module further comprises memory devices organized inranks, and each rank has a first portion of the memory devices thereinmounted on the first daughter board and a second portion of the memorydevices therein mounted on the second daughter board. The memory modulefurther comprises a first register device providing registered C/Asignals to memory devices mounted on the first daughter board, and asecond register device providing registered C/A signals to memorydevices mounted on the second daughter board.

In certain embodiment, each daughter board has a rigid portion and aflexible portion. Memory devices mounted on the rigid portion arecoupled to the main module board via flexible traces on the flexibleportion. The memory devices are organized in first, second and thirdranks. The rigid portion of each respective daughter board has a firstside and an opposing second side, and memory devices mounted on therespective daughter board include a first row of memory devices in thefirst rank mounted on a first side of the respective daughter board, asecond row of memory devices in the second rank mounted on the firstside of the respective daughter board, and a third row of memory devicesin the third rank mounted on a second side of the respective daughterboard.

In certain embodiments, the multi-rank memory module further comprisesmodule connectors along an edge of the main module board and data/strobesignal hubs on the first and second daughter boards. The moduleconnectors include data/strobe pins and each respective data/strobesignal hub is coupled to a respective one of the data/strobe pins and toa first memory device in the first rank, a second memory device in thesecond rank and a third memory device in the third rank. The respectivedata/strobe signal hub is positioned to reduce difference in lengths offirst, second and third signal paths, the first signal path between therespective data/strobe signal pin and the first memory device, thesecond signal path between the respective signal pin and the secondmemory device, and the third signal path between the respectivedata/strobe signal pin and the third memory device.

In yes another embodiment, a multi-rank memory module comprises a moduleboard, and module connectors along an edge of the module board via whichthe multi-rank memory module communicate respective bits of a datasignal. The memory module further comprises dual-die packages (DDP) eachincluding two stacked memory dies therein mounted the module board, andsingle-die packages (SDP) each having a single memory die thereinmounted on the module board. Each SDP corresponds to a respective DDPand is disposed on an opposing side of the module board from therespective DDP. The each SDP and the respective DDP are coupled to asame subset of module connectors for communicating a subset of data bitsof the data signal. The memory module further comprises at least oneregister device mounted on the module board and providing registered C/Asignals to memory dies.

In certain embodiments, the at least one register comprises a firstregister device providing registered C/A signals to the DDPs and devicea second register device providing registered C/A signals to thesingle-die packages.

In certain other embodiments, the at least one register device includesa single register device providing registered C/A signals to the DDPsand the SDPs.

In certain embodiments, the registered C/A signals include first, secondand third chip select signals, and the memory die in the each SDP andthe memory dies in the respective DDP receive respective ones of thefirst, second and third chip select signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory system comprising a memorycontroller and a memory module coupled to a printed circuit boardaccording to embodiments.

FIGS. 2A and 2B are block diagrams illustrating arrangement of memorydevices on a memory module according to one embodiment of the presentdisclosure.

FIGS. 3A and 3B are zoomed in views of portions of a memory moduleaccording to an embodiment of the present disclosure.

FIG. 3C is a side view of a memory module illustrating dimensionsthereof according to one embodiment of the present disclosure.

FIG. 4A is a schematic diagram illustrating certain data signal hubs andsignal traces on a memory module according to an embodiment of thepresent disclosure.

FIG. 4B is a three-dimensional view of certain data signal hubs andsignal traces on a memory module according to an embodiment of thepresent disclosure.

FIG. 4C is a side view of a memory module illustrating certain datasignal hubs and signal traces thereon according to one embodiment of thepresent disclosure.

FIG. 4D is a schematic diagram of electrical connections between certainmemory devices and a respective module connector via a data signal huband signal traces according to one embodiment of the present disclosure.

FIG. 5A is a side view of a memory module illustrating arrangement ofmemory devices and certain data signal hubs and signal traces thereonaccording to an embodiment of the present disclosure.

FIG. 5B is a schematic diagram of electrical connections between certainmemory devices and a respective module connector via a data signal huband signal traces according to one embodiment of the present disclosure.

FIG. 5C is a block diagram illustrating memory device loads onregistered control/address signals in a memory module according to anembodiment of the present disclosure.

FIG. 6A is a side view of a memory module illustrating arrangement ofmemory devices and certain data signal hubs and signal traces thereonaccording to an embodiment of the present disclosure.

FIG. 6B is a schematic diagram of electrical connections between certainmemory devices and a respective module connector via a data signal huband signal traces according to one embodiment of the present disclosure.

FIG. 6C is a block diagram illustrating memory device loads onregistered control/address signals in a memory module having tworegister devices according to an embodiment of the present disclosure.

FIG. 6D is a block diagram illustrating memory device loads onregistered control/address signals in a memory module using a singleregister device according to an embodiment of the present disclosure.

DESCRIPTION OF EMBODIMENTS

As shown in FIG. 1, which illustrates a exemplary memory system 100having a memory controller 110 and a memory module 120 coupled to eachother by a memory bus 130. The memory module 120 includes at least onemodule board 122 and has a primary side (front side) 120 a and asecondary side (back side) 120 b, and memory devices 124 mounted on boththe primary side 120 a and the secondary side 120 b. The memory modulefurther includes module connectors 126 in the form of, for example,metal pins or pads formed on one or both sides of the module board andnear a bottom edge 128 of the module board. The memory controller can bemounted on a circuit board 140, and the memory bus 130 includes signallines, which can be signal traces on or in the circuit board 140. Themodule connectors are coupled to respective signal lines on the circuitboard by, for example, inserting the bottom edge 128 of the module boardinto a slot or socket 150 on the circuit board 140, which may includemetal contacts formed inside to facilitates connection of the moduleconnectors with the respective signal lines in the memory bus 130.

In one embodiment, the memory module 120 can be a multi-rank registeredDIMM (dual in-line memory module) compatible with the DDR3 (double datarate 3) standard published by JEDEC (the Joint Electron DevicesEngineering Council). The memory devices can be DRAM (dynamic randomaccess memory) devices, and the module board 122 can be a multi-layeredprinted circuit board. The present description may also apply to othertypes of memory modules and/or memory devices.

In the context of the present description, a rank refers to one or morememory devices that are selectable by a common chip-select (CL) signal,a memory controller refers to any device capable of sending instructionsor commands, or otherwise controlling the memory devices, and a memorybus refers to any component, connection, or groups of components and/orconnections, used to provide electrical communication between a memorymodule and a memory controller. For example, in various embodiments, thememory bus 105 may include printed circuit board (PCB) transmissionlines, one or more sockets, module connectors, component packages,and/or any other components or connectors that provide connections forsignal transmission.

FIGS. 2A and 2B are block diagrams of an exemplary memory module 120illustrating memory devices arranged on the primary (front) side 120 aand the secondary (back) side 120 b, respectively, of the memory module120. As shown, the memory module 120 according to one embodiment canhave 9×6=54 memory devices, U1 to U36 and U39-U56, organized in first,second and third ranks. For example, the first rank includes memorydevices U19-U36 on the back (secondary) side 120 b of the memory module120, which are selectable by a first chip select signal, the second rankincludes memory devices U1-U18 on the front (primary) side 120 a of thememory module 120, which are selectable by a second chip select signal,and the third rank includes memory devices U39-U47 on the primary side120 a and memory devices U48-U56 on the secondary side 120 b of themodule board 120, which are selectable by a third chip select signal.

In one embodiment, the memory devices in the first rank are arranged intwo rows, with memory devices U19-U27 arranged in a first row from aleft edge A of the module board 122 to a right edge A′ of the moduleboard 122, and memory devices U28-U36 arranged in a second row from theleft edge A of the module board 122 to the right edge A′ of the moduleboard 122. Likewise, the memory devices in the second rank are arrangedin two rows, with memory devices U1-U9 arranged in a third row from aleft edge A of the module board 122 to a right edge A′ of the moduleboard 122, and memory devices U10-U18 arranged in a fourth row from theleft edge A of the module board 122 to the right edge A′ of the moduleboard 122. The memory devices in the third rank are also arranged in tworows, with memory devices U39-U47 arranged in a fifth row from a leftedge A of the module board 122 to a right edge A′ of the module board122 on the front side 120 a, and memory devices U48-U66 arranged in asixth row from the left edge A of the module board 122 to the right edgeA′ of the module board 122 on the back side 120 b.

As also shown in FIGS. 2A and 2B, the memory module 120 further includestwo register devices U37 and U38 both disposed on the primary side ofthe module board 122 near a middle portion between the left edge A andthe right edge A′ of the module board 122. In one embodiment, one of theregister devices U37 and U38 provides control/address information to thefirst rank and the second rank, while the other one of the registerdevices U37 and U38 provides control/address information to the thirdrank. Other arrangements to allocate the memory devices with respect tothe register devices are also possible and consistent with the presentdescription. For example, in another embodiment, one of the registerdevices U37 and U38 provides control/address information to the secondrank and the other one of the register devices U37 and U38 providescontrol/address information to the first rank and the third rank.

In one embodiment, as shown in FIGS. 3A and 3B, which illustratesblown-up views of portions of the front side 120 a of the memory module120, the module board 122 has a bottom edge 128 and a top edge 302, thememory devices and the register devices include input/output (I/O) pins305 in the form of, for example, contact pads or solder balls, that areconnected to corresponding contact pads/pins or solder balls on themodule board 122. Memory module 120 further includes module connectors126 disposed near the bottom edge 128 of the module board. The memorymodule 120 may also include discrete components such as capacitors andresisters disposed on the one or both sides of the module board, as alsoillustrated in FIGS. 3A and 3B.

In one embodiment, the module board 122 is a multi-layered PCB board(e.g., 12-layered PCB board). The memory module has a height (distancebetween the bottom edge 128 and the top edge 302) equal to or less thanabout 47 mm. In a further embodiment, the height is about 46.5 mm. In afurther embodiment, as shown in FIG. 3C, the height is about 40.7 mm.Reduction in height is made possible by placing both of the registerdevices U37 and U38 on the primary side 120 a of the memory module 120.Placing both of the register devices U37 and U38 on the primary side 120a also results in improved signal integrity and better routing of signallines/traces and placement of discrete components in/on the module boardfor this multi-rank memory module.

The module connectors 126 include input/output (I/O) pins such asdata/strobe pins, via which data/strobe signals are communicated betweenthe memory devices and the memory controller 110, and control/address(C/A) pins, via which C/A signals are received from the memorycontroller 110. For example, in one embodiment, the module connectors126 include the following I/O pins disposed near the bottom edge 128 ofthe module board 122 on the front side 120 a, arranged from the leftedge A of the module board 122 to the right edge A′ of the module board122 in the order of, for example: DQ0, DQ1, DQS0#, DQS0, DQ2, DQ3, DQ8,DQ9, DQS1#, DQS1, DQ10, DQ11, DQ16, DQ17, DQS2#, DQS2, DQ18, DQ19, DQ24,DQ25, DQS3#, DQS3, DQ26, DQ27, CB0, CB1, DQS8#, DQS8, CB2, CB3, CKE0,BA2, ERROUT#, A11, A7, A5, A4, A2, CK1, CK1#, PAR_IN, A10, BA0, WE, CAS,CS1, ODT1, CS2, DQ32, DQ33, DQS4#, DQS4, DQ34, DQ35, DQ40, D41, DQS5#,DQS5, DQ42, DQ43, DQ48, DQ49, DQS6#, DQS6, DQ50, DQ51, DQ56, DQ57,DQS7#, DQS7, DQ58, DQ59, SA0, SCL, SA2.

The module connectors 126 also include the following I/O pins disposednear the bottom edge 128 of the module board 122 on the back side 120 b,arranged from the left edge A of the module board 122 to the right edgeA′ of the module board 122, in the order of, for example: DQ4, DQ5,DQS9#, DQS9, DQ6, DQ7, DQ12, DQ13, DQS10, DQS10#, DQ14, DQ15, DQ20,DQ21, DQS11, DQS11#, DQ22, DQ23, DQ28, DQ29, DQS12, DQS12#, DQ30, DQ31,CB4, CB5, DQS17, DQS17#, CB6, CB7, MCLR, RESET#, CKE1, A15, A14, A12,A9, A8, A6, A3, A1, CK0, CK0#, A0, BA1, RAS, CS0, ODT0, A13, CS3, DQ36,DQ37, DQS13, DQS13#, DQ38, DQ39, DQ44, D45, DQS14, DQS14#, DQ46, DQ47,DQ52, DQ53, DQS15, DQS15#, DQ54, DQ55, DQ60, DQ61, DQS16, DQS16#, DQ62,DQ63, SA1, SDA.

In one embodiment, the register devices, U37 and U38, generateregistered control/address (C/A) signals based on control/address (C/A)signals received from the memory controller via respective moduleconnectors 126 and provide the registered C/A signals to the memorydevices via signal traces on/in the module board 122.

For example, the register device U37A receives row/column addresssignals from the memory controller 110 via C/A pins A0 through A15 andcorresponding I/O pins 305 of the register device U37A. The registerdevice U37A also receives bank address signals from the memorycontroller 110 via C/A pins BA0 through BA2 and corresponding I/O pins305 of the register device U37A. The register device U37A furtherreceives control signals RAS (row address strobe), CAS (column addressstrobe), WE (write enable), CS0, CS1, CKE0 (clock enable), CKE1, ODT0(on-die termination), etc. from the memory controller 110 viacorresponding C/A pins and corresponding I/O pins of the register deviceU37A.

In response, the register device U37A outputs registered C/A signals viacorresponding I/O pins of the register device U37A. In a furtherembodiment, the register device outputs two identical sets of registeredC/A signals, one toward the left edge A of the module board and onetoward the right edge A′ of the module board. The first set of the twoidentical sets of registered C/A signals include, for example,registered row/column address signals A0A, A1A, . . . , A15A, registeredbank address signals BA0A, BA1A, and BA2A, and registered controlsignals RASA, CASA, WEA, CS0A, CS1A, CKE0A, CKE1A, ODT0A. The second setof the two identical sets of registered C/A signals include, forexample, registered row/column address signals A0B, A1B, . . . , A15B,registered bank address signals BA0B, BA1B, and BA2B, and registeredcontrol signals RASB, CASB, WEB, CS0B, CS1B, CKE0B, CKE1B, ODT0B.

Similarly, the register device U38A receives row/column address signalsfrom the memory controller 110 via C/A pins A0 through A15 and viacorresponding I/O pins of the register device U38A. The register deviceU38A also receives bank address signals from the memory controller 110via C/A pins BA0 through BA2 and corresponding I/O pins of the registerdevice U38A. The register device U38A further receives control signalsRAS (row address strobe), CAS (column address strobe), WE (writeenable), CS0, CS1, CKE0 (clock enable), CKE1, ODT0 (on-die termination),etc. from the memory controller 110 via corresponding C/A pins andcorresponding I/O pins of the register device U38A.

In response, the register device U38A outputs registered C/A signals viacorresponding I/O pins of the register device U38A. In a furtherembodiment, the register device outputs two identical sets of registeredC/A signals, one toward the left edge A of the module board and onetoward the right edge A′ of the module board. The first set of the twoidentical sets of registered C/A signals may include, for example,registered row/column address signals A0A_2, A1A_2, . . . , A15A_2,registered bank address signals BA0A_2, BA1A_2, and BA2A_2, andregistered control signals RASA_2, CASA_2, WEA_2, CS2A, CKE2A, ODT1A.The second set of the two identical sets of registered C/A signals mayinclude, for example, registered row/column address signals A0B_2,A1B_2, . . . , A15B_2, registered bank address signals BA0B_2, BA1B_2,and BA2B_2, and registered control signals RASB_2, CASB_2, WEB_2, CS2B,CKE2B, ODT1B.

In one embodiment, each respective memory device on the memory module120 receives a set of registered C/A signals from one of the registerdevices and, in response thereto, communicate corresponding bits of dataand strobe signals with the memory controller 110 via correspondingdata/strobe pins of the memory module and corresponding I/O pins of therespective memory device. In one embodiment, each data pin correspond toa corresponding data bit of a data signal, which can be, for example,72-bit wide or 64-bit wide with or without error correction bits,respectively. In one embodiment, each memory device is 4-bit wide, and arespective group of three memory devices, one from each of the threeranks, correspond to 4 respective data pins.

For example, a first group of memory devices include memory device U1from the second rank, memory device U19 from the first rank, and memorydevice U39 from the third rank. Memory device U1 receives the first setof registered C/A signals output by the register device 37A except thechip select signal CS0A and in response communicate corresponding dataand strobe bits via data/strobe pins DQ0 DQ1, DQ2, DQ3, DQS0, and DQS0#with the memory controller 110; memory device U19 receives the first setof registered C/A signals output by the register device 37A except thechip select signal CS1A and in response communicate data and strobesignals via data/strobe pins DQ0 DQ1, DQ2, DQ3, DQS0, and DQS0# with thememory controller 110; and memory device U39 receives the first set ofregistered C/A signals output by the register device 38A and in responsecommunicate data and strobe signals via data/strobe pins DQ0 DQ1, DQ2,DQ3, DQS0, and DQS0# with the memory controller 110.

Also, a second group of memory devices include memory device U10 fromthe second rank, memory device U28 from the first rank, and memorydevice U48 from the third rank. Memory device U10 receives the first setof registered C/A signals output by the register device 37A except thechip select signal CS0A and in response communicate corresponding dataand strobe bits via data/strobe pins DQ4 DQ5, DQ6, DQ7, DQS9, and DQS9#with the memory controller 110; memory device U28 receives the first setof registered C/A signals output by the register device 37A except thechip select signal CS1A and in response communicate data and strobesignals via data/strobe pins DQ4 DQ5, DQ6, DQ7, DQS9, and DQS9# with thememory controller 110; and memory device U48 receives the first set ofregistered C/A signals output by the register device 38A and in responsecommunicate data and strobe signals via data/strobe pins DQ4 DQ5, DQ6,DQ7, DQS9, and DQS9# with the memory controller 110.

Each memory device receives the corresponding registered C/A signalsfrom one of the register devices via signal lines in the form of, forexample, board traces. Further, each memory device is also coupled tothe respective data/strobe pins via signal lines in the form of, forexample, board traces.

In certain embodiments, memory module 200 includes contact hubs (such ascontact hubs 401 and 402 shown in FIG. 4A) that are positioned away fromthe bottom edge 128 of the module board 122, and signal lines (such asboard traces 411 to 412 shown in FIG. 4A) connecting the respectivecontact hubs to corresponding ones of the data/strobe pins 126. Thecontact hubs can be, for example, metal pads or solder balls disposed onor near the primary side or secondary side of the memory module 120,and/or vias in the module board 122.

In one embodiment, each contact hub is coupled to a corresponding I/Opin of each of a group of memory devices including one memory devicefrom each of the ranks. For example, as shown in FIG. 4, in which soliddots 415 represent contact pins on memory devices disposed on theprimary side 120 a of the memory module 120 and empty dots 416 representcontact pins on memory devices disposed on the secondary side 120 b ofthe memory module 120, contact hub 401 is coupled via star traces 421 toa corresponding contact pin of memory device U1 in the second rank, acorresponding contact pin of memory device U19 in the first rank, and acorresponding contact pin of memory device U39 in the third rank.

Similarly, as also shown in FIG. 4A, contact hub 402 is coupled via startraces 422 to a corresponding contact pin of memory device U10 in thesecond rank, a corresponding contact pin of memory device U28 in thefirst rank, and a corresponding contact pin of memory device U48 in thethird rank.

Thus, memory devices are connected to the module connectors 126 via thecontact hubs and multiple memory devices can be coupled to therespective module connectors via a same set of signal traces on/in themodule board 201. For example, as shown in FIG. 4A, memory devices U1,U19, and U39 are coupled to the module connector for DQ0 via a samecontact hub 401 and a same signal trace 411.

In one embodiment, each of the contact hubs is positioned to reducedifference in lengths of the signal paths between respective ones of thememory devices coupled thereto and a corresponding module connector. Forexample, as shown in FIG. 4A, contact hub 401 is positioned to bebetween memory devices U1 and U39 and closer to memory device U39 inorder to reduce differences in the signal path lengths via the startraces 421, resulting in reduced differences in the signal path lengthsfrom memory devices U1, U19, and U39 to each of the module pins forDQ[0:3], DQS0 and DQS0#.

Similarly, as shown in FIG. 4B, contact hub 402 is positioned to bebetween memory devices U48 and U28 and closer to memory device U28 inorder to reduce differences in the signal path lengths via the startraces 422, so as to reduce differences in the signal path lengths frommemory devices U10, U28, and U48 to each of the module pins for DQ[4:7],DQS9 and DQS9#.

Further, one or more of the signal traces 411 and 412 may be routed toreduce a difference in length therebetween. As also shown in FIG. 4A,since the contact hub 402 is closer to the bottom edge 128 of the moduleboard 201 than the contact hub 401, the signal trace 412 is routed tomake it significantly longer than the distance between the contact hub402 and the bottom edge 128 of the module board so as to reduce thedifference in lengths between signal trace 411 and signal trace 412.Thus, as shown in FIG. 4A, instead of using a straighter path betweenmodule connector for DQ4 and contact hub 402, a more circuitous routefor the signal trace 412 is used.

In one embodiment, as shown in FIG. 4B, one or more of the star traces421 may include at least one via 421 a and at least one signal trace 421b in at least one different layer of the module board from the otherones of the star traces 421 in order to reach the memory device on aside of the module board that is different from the side on which thecontact hub 401 is disposed, or to which the contact hub 401 is closer.In one embodiment, contact hub 401 is disposed on or is closer to theprimary side 120 a of the memory module 120.

Likewise, one or more of the star traces 422 may include at least onevia 422 a and at least one signal trace 422 b in at least one differentlayer of the module board in order to reach the memory device on a sideof the module board that is different from the side on which the contacthub 402 is disposed, or to which the contact hub 402 is closer. In oneembodiment, contact hub 402 is disposed on or is closer to the secondaryside 120 b of the memory module 120.

The signal traces shown in FIGS. 4A and 4B are exaggerated andstraightened for ease of illustration. In practice the signal lines ortraces between the module connectors and the contact hubs, and betweenthe contact hubs and the input/output pins of the memory devices arerouted around various contacts and/or vias on/in the module board. Eachof these traces may include multiple sections in different layers of themodule board and may include one or more vias.

FIG. 4C is a side view of the memory module 120 and FIG. 4D is aschematic diagram illustrating electrical couplings between thedata/strobe pin DQ0 and memory devices U1, U19, and U39. As shown inFIG. 4D, the signal trace 411 can include one or more board traces 411 ain the same or different layers, one or more vias 411 b, and one or morediscrete component 411 c.

In certain embodiments, the memory module 120 can include more than onemodule boards, and the memory devices can be arranged differently. Forexample, the memory module 120 can utilize the planar-X technologydisclosed in commonly-owned co-pending U.S. patent application Ser. No.13/653,254, entitled “Circuit with Flexible Portion,” filed on Oct. 16,2012, and U.S. patent application Ser. No. 13/731,034, entitled “ModuleHaving at Least One Thermally Conductive Layer between Printed CircuitBoards,” filed on Dec. 30, 2012, each of which is incorporated byreference herein in its entirety. The planar-X technology can provide amore symmetric topology for a 3-ranked memory module with significantlyshorter vertical dimension.

As shown in FIG. 5A, the memory module 120 can have a main module board122 a and two daughter boards 122 b and 122 c each having a flexibleportion 500 having flexible traces that are coupled respectively tocorresponding contacts 501 on the main module board 122 a. Some of thememory devices, such as the first group of memory devices U1, U19, andU39 are mounted on the daughter board 122 b, and some of the memorydevices, such as the second group of memory devices U10, U28, and U48are mounted on the daughter board 122 c. These memory devices arecoupled via signal traces on the daughter boards and the main moduleboard to the module connectors 126 near the bottom edge 128 of the mainmodule board 122 a, as shown in FIG. 5A.

For example, as shown in FIG. 5A, the first group of memory devices arecoupled to a corresponding data/strobe pin (e.g., DQ0) among the moduleconnectors 126 near the bottom edge 128 of the main module board 122 avia star traces 421, contact hub 401, signal trace 411 on the daughterboard 122 b, a corresponding flexible trace on the flexible portion 501,and a corresponding trace on the main module board 122 a. FIG. 5B is aschematic diagram illustrating electrical couplings between thedata/strobe pin and memory devices U1, U19, and U39.

FIG. 5C is a top view of the planar-X multi-rank memory module shown inFIG. 5A, illustrating arrangement of the memory devices 510 and oneregister 520 on one side of a daughter board 500, which can be eitherone of the daughter boards 122 b and 122 c. As shown, the register 520outputs two sets of registered C/A signals, one toward a left side A ofthe daughter board 500 and one toward the right side A′ of the daughterboard 500. The two sets of registered C/A signals are similar to thoseoutput by register 37A described above except that each set ofregistered C/A signals would include three chip select signals CS0, CS1and CS2 instead of two chip select signals CS0 and CS1. Some of the C/Asignals such as the chip select signals are provided respectively tomemory devices in different ranks.

The set of registered C/A signals toward the left edge A are output viaeach of two sets of C/A signal line 530 a and 530 b to the memorydevices 510 disposed between the left edge A and the register device520. Likewise, the set of registered C/A signals toward the right edgeA′ are output via each of two sets of C/A signal line 530 c and 530 d tothe memory devices 510 disposed between the left edge A and the registerdevice 520. Thus, the set of signal lines 530 b would have twice theamount of memory device load as the set of signal lines 530 a. Likewise,the set of signal lines 530 d would have twice the amount of memorydevice load as the set of signal lines 530 c. Although thisconfiguration may result in asymmetric loading for registered C/Asignals from the registers, with proper termination, good signal qualityfor the registered C/A signals can be achieved. Note that because tworegister devices are used, this configuration would result in tworegister device loads for each pre-registered C/A signal from the memorycontroller.

FIG. 6A illustrates a planar design for a 3-ranked RDIMM (registereddual in-line memory module) 120 according to embodiments. As shown inFIG. 6A, the 3-ranked RDIMM 120 includes a module board 122, anddual-die packages (DDP) on one side of the module board and single diepackages (SDP) on opposite side of the module board 122. This placementcan create asymmetric data lines, as the DRAMs located closer to thebottom edge 128 of the module board 122 would have shorter trace lengthcompared to the DRAMs located along the top edge of the module board122. Also data signals communicated with the DDP would have higherloading compared to data signals communicated with the SDP, as shown inFIG. 6B.

FIG. 6C is a top view of the 3-ranked RDIMM shown in FIG. 6A, whichutilizes two register devices 602, one on each side of the module board122 to drive the DRAMs on the same side of the module board. Theinput/output signals of register 602 on the same side of the DDPs can bethe same or similar to the register 37U, and the input/output signals ofregister 602 on the same side of the SDPs can be the same or similar tothe register 38U. In such a configuration, the output of each registerwould have fairly balanced loading for the registered C/A signals. Theregister device on the same side of the DDP's, however, would drivetwice the number of DRAMs than the register device on the opposite sideof the module board. Higher number of resisters can be used to terminateall registered C/A signals to insure good signal quality. Again, thisconfiguration would result in two loads for each pre-registered C/Asignal.

FIG. 6D is a top view of the 3-ranked RDIMM shown in FIG. 6A, whichutilized only one register device 602 on one side of the module board122, e.g., the same side of the module board as the DDP's. This registerdevice 602 can be similar to the register 520 (e.g., outputting threechip select signals) and would drive the DRAMs on both sides of themodule board 122. This configuration would result in symmetrical loadingfor the registered C/A signals and one memory device load for eachpre-registered C/A signal. It should be more suited for high-speedoperation with two DIMM per channel.

We claim:
 1. A multi-rank memory module, comprising: a module boardhaving a first side and an opposing second side; and memory devicesorganized in first, second and third ranks, wherein memory devices inthe first rank are all mounted on the first side, memory devices in thesecond rank are all mounted on the second side, and memory devices inthe third rank include a first number of memory devices mounted on thefirst side, and include a second number of memory devices mounted on thesecond side.
 2. The multi-rank memory module of claim 1, furthercomprising: module connectors along an edge of the module board,including data/strobe signal pins and control/address (C/A) signal pins;and data/strobe signal hubs, wherein a respective data/strobe signal hubis coupled to a respective data/strobe signal pin and to a respectiveset of first, second and third memory devices in different ranks, andwherein the respective data/strobe signal hub is positioned to reducedifference in lengths of first, second and third signal paths, the firstsignal path between the respective data/strobe signal pin and the firstmemory device, the second signal path between the respective signal pinand the second memory device, and the third signal path between therespective data/strobe signal pin and the third memory device.
 3. Themulti-rank memory module of claim 2, wherein the data/strobe signal hubsinclude a first signal hub and a second signal hub coupled to respectiveones of first data/strobe signal pin and second data/strobe signal pin,the multi-rank memory module further comprising a first signal tracebetween the first data/strobe signal pin and the first signal hub, and asecond signal trace between the second data/strobe signal pin and thesecond signal hub, one of the first and second signal traces beingrouted to increase its length so as to reduce difference in lengthsbetween the first signal trace and the second signal trace.
 4. Themulti-rank memory module of claim 2, further comprising: at least oneregister device mounted on the first side, the at least one registerdevice receiving C/A signals from the memory controller via the C/Asignal pins and providing registered C/A signals to the memory devices.5. The multi-rank memory module of claim 4, wherein the at least oneregister includes a first register providing registered C/A signals tomemory devices in the first rank and second rank, and a second registerproviding registered C/A signals to memory devices in the third rank. 6.The multi-rank memory module of claim 2, further comprising resistersdisposed close to the data/strobe signal pins, wherein the respectivedata/strobe signal hubs is positioned closer to the first, second andthird memory devices than to any of the resisters.
 7. The memory moduleof claim 1, wherein the memory devices in the third rank include a firstrow of memory devices mounted on the first side and a second row ofmemory devices mounted on the second side.
 8. The memory module of claim7, further comprising module connectors along an edge of the moduleboard, including data/strobe signal pins and control/address (C/A)signal pins; wherein the memory devices in the first rank include athird row of memory devices mounted on the first side and a fourth rowof memory devices mounted on the first side, the third row of memorydevices being closer to the module connectors than the fourth row ofmemory device, and wherein the first row of memory devices are disposedbetween the third row of memory devices and the fourth row of memorydevices.
 9. The memory module of claim 7, wherein the memory devices inthe second rank include a fifth row of memory devices mounted on thesecond side and a sixth row of memory devices mounted on the secondside, the fifth row of memory devices being closer to the moduleconnectors than the sixth row of memory devices, and wherein the secondrow of memory devices are disposed between the fifth row of memorydevices and the sixth row of memory devices.
 10. The memory module ofclaim 9, wherein a first memory device in the first row of memorydevices, a second memory device in the third row of memory devices, anda third memory device in the fifth row of memory devices communicatedata with the memory controller through a same first set of data lines.11. The memory module of claim 10, wherein a fourth memory device in thesecond row of memory devices, a fifth memory device in the fourth row ofmemory devices, and a sixth memory device in the sixth row of memorydevices communicate data with the memory controller through a samesecond set of data lines.